{"id":138,"date":"2017-03-10T16:07:11","date_gmt":"2017-03-10T15:07:11","guid":{"rendered":"http:\/\/setsis.uca.fr\/?page_id=138"},"modified":"2022-10-19T13:18:47","modified_gmt":"2022-10-19T11:18:47","slug":"programme","status":"publish","type":"page","link":"http:\/\/setsis.eupi.uca.fr\/?page_id=138","title":{"rendered":"Programme"},"content":{"rendered":"

Le Master SETSIS se d\u00e9roule sur 2 ann\u00e9es universitaires soit 4 semestres repr\u00e9sentant  60 ECTS (Cr\u00e9dits europ\u00e9ens).<\/span><\/p>\n

Toutes les mati\u00e8res sont d\u00e9taill\u00e9es dans<\/strong><\/span> ici<\/strong><\/a><\/h4>\n

Master 1 :<\/span><\/strong><\/span>\n\n\n\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t
Semestre 1<\/td>Cr\u00e9dits<\/td>Cours<\/td>TD <\/td>TP<\/td>\n<\/tr>\n
Culture d'entreprise<\/td>3<\/td>14<\/td>16<\/td><\/td>\n<\/tr>\n
Programmation C \/ C++<\/td>3<\/td>6<\/td><\/td>24<\/td>\n<\/tr>\n
Optimisation lin\u00e9aire et application aux r\u00e9seaux de neurones<\/td>3<\/td>6<\/td>7,5<\/td>16,5<\/td>\n<\/tr>\n
Microcontr\u00f4leurs<\/td>3<\/td>6<\/td>6<\/td>18<\/td>\n<\/tr>\n
Apprentissage et Deep learning<\/td>3<\/td>12<\/td>6<\/td>12<\/td>\n<\/tr>\n
Gestion de projets informatiques<\/td>3<\/td>8<\/td>10<\/td>16<\/td>\n<\/tr>\n
Traitement d\u2019images et Vision par ordinateur (en commun avec Polytech)<\/td>3<\/td>10,5<\/td><\/td>31,5<\/td>\n<\/tr>\n
Traitement du signal<\/td>6<\/td>13<\/td>14<\/td>27,5<\/td>\n<\/tr>\n
Stockage et transfert de donn\u00e9es (en commun avec Polytech)<\/td>3<\/td>10<\/td>4<\/td>12<\/td>\n<\/tr>\n
TOTAL<\/td>30<\/td>85,5<\/td>63,5<\/td>157,5<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n<\/span><\/p>\n

\n\n\n\n\t\n\t\n\t\n\t\n\t\n\t\n\t
Semestre 2<\/td>Cr\u00e9dits<\/td>CM<\/td>TD<\/td>TP<\/td>\n<\/tr>\n
Anglais<\/td>3<\/td><\/td>20<\/td><\/td>\n<\/tr>\n
D\u00e9veloppement terminal mobile et objets connect\u00e9s<\/td>3<\/td>9<\/td>9<\/td>12<\/td>\n<\/tr>\n
Stage ou TER<\/td>18<\/td><\/td><\/td><\/td>\n<\/tr>\n
VHDL et Programmation de FPGA<\/td>3<\/td>16<\/td>14<\/td><\/td>\n<\/tr>\n
C++ avanc\u00e9 et programmation parall\u00e8le<\/td>3<\/td>9<\/td>9<\/td>12<\/td>\n<\/tr>\n
Total<\/td>30<\/td>34<\/td>52<\/td>12<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n<\/span><\/p>\n

Master 2:<\/span><\/strong><\/span>\n\n\n\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t
Semestre 3<\/td>Cr\u00e9dits<\/td>CM<\/td>TD<\/td>TP<\/td>\n<\/tr>\n
Anglais<\/td>3<\/td><\/td>19.5<\/td><\/td>\n<\/tr>\n
Culture d'entreprise<\/td>3<\/td><\/td>30<\/td><\/td>\n<\/tr>\n
Librairies d\u00e9veloppement Image<\/td>3<\/td>6<\/td>8<\/td>16<\/td>\n<\/tr>\n
Conception conjointe : mat\u00e9rielle et logicielle (en commun avec Polytech)<\/td>3<\/td>12<\/td><\/td>18<\/td>\n<\/tr>\n
VHDL avanc\u00e9 pour la synth\u00e8se FPGA <\/td>3<\/td>14<\/td><\/td>16<\/td>\n<\/tr>\n
Linux embarqu\u00e9<\/td>3<\/td>14<\/td><\/td>16<\/td>\n<\/tr>\n
Traitement et mastering du son<\/td>3<\/td>10<\/td>8<\/td>12<\/td>\n<\/tr>\n
Traitement du signal sur cibles mat\u00e9rielles reconfigurables<\/td>3<\/td>9<\/td><\/td>21<\/td>\n<\/tr>\n
Traitement d'images et vision par ordinateur avanc\u00e9e<\/td>3<\/td>22<\/td><\/td>8<\/td>\n<\/tr>\n
Mod\u00e9lisation System C (en commun avec Polytech)<\/td>3<\/td>22<\/td><\/td>8<\/td>\n<\/tr>\n
TOTAL<\/td>30<\/td>109<\/td>65.5<\/td>115<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n<\/span><\/p>\n

\n\n\n\n\t\n\t\n\t\n\t\n\t\n\t
Semestre 4<\/td>Cr\u00e9dits<\/td>CM<\/td>TD<\/td>TP<\/td>\n<\/tr>\n
TP de synth\u00e8se<\/td>3<\/td><\/td><\/td>30<\/td>\n<\/tr>\n
architecture pour le traitement d'image et l'IA<\/td>3<\/td>12<\/td>6<\/td>12<\/td>\n<\/tr>\n
Programmation GPU - Initiation \u00e0 CUDA pour l'IA<\/td>3<\/td>8<\/td><\/td>22<\/td>\n<\/tr>\n
Stage<\/td>21<\/td><\/td><\/td><\/td>\n<\/tr>\n
TOTAL<\/td>30<\/td>20<\/td>6<\/td>64<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n<\/span><\/p>\n","protected":false},"excerpt":{"rendered":"

Le Master SETSIS se d\u00e9roule sur 2 ann\u00e9es universitaires soit 4 semestres repr\u00e9sentant  60 ECTS (Cr\u00e9dits europ\u00e9ens). Toutes les mati\u00e8res sont d\u00e9taill\u00e9es dans ici Master 1 : Master 2:<\/p>\n","protected":false},"author":1,"featured_media":0,"parent":0,"menu_order":0,"comment_status":"closed","ping_status":"closed","template":"","meta":{"footnotes":""},"class_list":["post-138","page","type-page","status-publish","hentry"],"_links":{"self":[{"href":"http:\/\/setsis.eupi.uca.fr\/index.php?rest_route=\/wp\/v2\/pages\/138"}],"collection":[{"href":"http:\/\/setsis.eupi.uca.fr\/index.php?rest_route=\/wp\/v2\/pages"}],"about":[{"href":"http:\/\/setsis.eupi.uca.fr\/index.php?rest_route=\/wp\/v2\/types\/page"}],"author":[{"embeddable":true,"href":"http:\/\/setsis.eupi.uca.fr\/index.php?rest_route=\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"http:\/\/setsis.eupi.uca.fr\/index.php?rest_route=%2Fwp%2Fv2%2Fcomments&post=138"}],"version-history":[{"count":18,"href":"http:\/\/setsis.eupi.uca.fr\/index.php?rest_route=\/wp\/v2\/pages\/138\/revisions"}],"predecessor-version":[{"id":582,"href":"http:\/\/setsis.eupi.uca.fr\/index.php?rest_route=\/wp\/v2\/pages\/138\/revisions\/582"}],"wp:attachment":[{"href":"http:\/\/setsis.eupi.uca.fr\/index.php?rest_route=%2Fwp%2Fv2%2Fmedia&parent=138"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}